NXP i.MX 8M Plus
The EdgeFirst Profiler runs on the NXP i.MX 8M Plus (aarch64) and uses the VeriSilicon (VSI) NPU for hardware-accelerated inference, exposed through the TFLite C library and the libvx_delegate.so shared object.
For a guided platform tour see the i.MX 8M Plus Quick Start. This page covers only the profiler-specific setup.
Prerequisites
- NXP Linux BSP image with the EdgeFirst SDK overlay
libtensorflowlite_c.so(preinstalled)libvx_delegate.so(preinstalled)
The i.MX 8M Plus VSI NPU runs standard TFLite models — no model rewrite is required, unlike the i.MX 95 Neutron NPU. Quantize the model to int8 for best performance; floating-point graphs fall back to CPU.
Install the profiler
pip install edgefirst-profiler
curl -fsSL https://raw.githubusercontent.com/EdgeFirstAI/profiler-cli/main/install.sh | bash
Confirm:
edgefirst-profiler --version
Delegate selection
| Value | Behavior on i.MX 8M Plus |
|---|---|
(omitted) / auto |
Auto-detects i.MX 8M Plus from device-tree compatible string and loads libvx_delegate.so. |
xnnpack |
CPU baseline. |
none / cpu |
Reference kernels only. |
path to .so |
Custom delegate. |
Pipeline depth
The VSI delegate supports only one in-flight inference at a time. The profiler detects this and clamps --pipeline-depth down to a single inference slot — CPU stages (decode, postprocess, encode) still overlap with the single inference, but two inferences cannot run concurrently on the NPU.
The Studio trace view makes this serialization visible — back-to-back invoke slices touch but never overlap.
See the Pipelining concept page for the full backend table, the sequential vs. pipelined mental model, and how each mode appears in the trace viewer.
Verifying the install
edgefirst-profiler login
edgefirst-profiler # F4 Profiler should show /usr/lib/libvx_delegate.so auto-filled
Then run a validation session — see Validation from Studio or Validation from the Profiler.